Clock signal detection circuit and semiconductor integrated circuit using the same

ABSTRACT

A clock signal detection circuit is provided that can reliably detect whether or not a clock signal is supplied with a reduced circuit scale and reduced power consumption. The clock signal detection circuit comprises: a tristate buffer circuit that generates an output signal of predetermined potential when a clock signal is in a first level, and that sets the output terminal to the high impedance state when the clock signal is in a second level; a resistor disposed between the output terminal of the tristate buffer circuit and a different potential from the predetermined potential; and a buffer circuit that generates a clock signal detection result in accordance with the output potential of the tristate buffer circuit,

RELATED APPLICATIONS

[0001] The present application claims priority to Japanese PatentApplication No, 2003-115248 filed Apr. 21, 2003 which is herebyexpressly incorporated by reference herein in its entirety.

BACKGROUND

[0002] 1. Field of the Invention

[0003] The present invention relates to a clock signal detection circuitthat detects whether or not a clock signal is supplied thereto andfurther to a semiconductor integrated circuit using such a clock signaldetection circuit,

[0004] 2. Description of the Related Art

[0005] Semiconductor integrated circuits for handling digital signalscommonly contain many circuits that operates in sync with a clocksignal, such as a flip-flop circuit. In order to detect whether or notthe clock signal is supplied to such a circuit, clock detection circuitsare sometimes used in such semiconductor integrated circuits,

[0006] Conventional clock signal detection circuits sample a targetclock signal based on a reference clock signal to detect whether or nota level of the target clock signal changes, However, this is problematicin that a large-scale circuit is necessary to perform such detectioncausing large power consumption, Moreover, the reliability of detectionis not very high,

[0007] Incidentally, in Japanese unexamined patent publication No,10-123996 (Pages 1 and 5, FIG. 1), a bolometer-type infrared ray sensoris described as an example of a semiconductor device equipped with apixel protection circuit. This bolometer-type infrared ray sensorconsistently watches a plurality of data signals and clock signals inputthereto by respective monitoring circuit, thus preventing the pixel frombeing selected by turning off a switch if a scanning circuit stops oroperates improperly because of, for example, disconnection of thesesignals,

[0008] In the bolometer-type infrared ray sensor, a horizontal clockmonitoring circuit comprises a retriggerable monostable multivibrator.The horizontal clock monitoring circuit outputs a signal for enabling ahorizontal switch to select pixels if a horizontal clock signal iscontinuously input, but if the horizontal clock stops, the horizontalclock monitoring circuit outputs a signal for making the horizontalswitch move to a shut-down state after a time constant determined by acapacitor and a resistor has elapsed, thus protecting the device bypreventing pixels from being deteriorated in quality or broken,

[0009] Here, the time constant determined by the capacitor and resistoris selected to a time duration throughout which any specific one of thepixels can be continuously selected without any deterioration in qualityor breaking-down of the pixel caused by self-heating of a bolometer.However, monostable multivibrators have a large circuit scale andaccordingly require large power consumption, Furthermore, if a capacitoris formed inside a semiconductor integrated circuit, a particularlylarge area is necessary among passive elements because the capacitor hasa structure of two parallel electrodes holding a dielectric materialtherebetween.

[0010] Consequently, taking the above into consideration, the presentinvention advantageously provides a clock signal detection circuit and asemiconductor integrated circuit using the same clock signal detectioncircuit that is able to reliably detect whether or not a clock signal issupplied thereto with a reduced circuit scale and reduced powerconsumption.

SUMMARY

[0011] In order to solve the above problems, a clock signal detectioncircuit according to a first aspect of the present invention comprises:a first circuit for generating an output signal of predeterminedpotential in accordance with a first level of a clock signal, and forsetting an output terminal to the high impedance state in accordancewith a second level of the clock signal; an impedance element disposedbetween the output terminal of the first circuit and a potentialdifferent from the predetermined potential; and a second circuit forgenerating a clock signal detection result in accordance with the outputpotential of the first circuit.

[0012] A clock signal detection circuit according to a second aspect ofthe present invention comprises: a first circuit for generating anoutput signal of predetermined potential in accordance with a firstlevel of a clock signal, and for setting an output terminal to the highimpedance state in accordance with a second level of the clock signal; afirst impedance element disposed between the output terminal of thefirst circuit and a potential different from the predeterminedpotential; a second circuit for generating an output signal inaccordance with the output potential of the first circuit; a thirdcircuit for generating an output signal of the predetermined potentialin accordance with a second level of a clock signal, and for setting anoutput terminal to the high impedance state in accordance with a firstlevel of the clock signal; a second impedance element disposed betweenthe output terminal of the third circuit and a potential different fromthe predetermined potential; a fourth circuit for generating an outputsignal in accordance with the output potential of the third circuit; anda fifth circuit for generating a clock signal detection result based onthe output signals of the second and the fourth circuit.

[0013] In the above circuits, the impedance elements can include aresistor or a capacitor.

[0014] Furthermore, a semiconductor integrated circuit according to afirst aspect of the present invention comprises: a first circuit forgenerating an output signal of a predetermined potential in accordancewith a first level of a clock signal, and for setting an output terminalto the high impedance state in accordance with a second level of theclock signal; and a second circuit for generating a clock signaldetection result in accordance with the output potential of the firstcircuit with an impedance element disposed between the output terminalof the first circuit and potential different from the predeterminedpotential.

[0015] A semiconductor integrated circuit according to a second aspectof the present invention comprises: a first circuit for generating anoutput signal of a predetermined potential in accordance with a firstlevel of a clock signal, and for setting an output terminal to the highimpedance state in accordance with a second level of the clock signal; asecond circuit for generating an output signal in accordance with theoutput potential of the first circuit with a first impedance elementdisposed between the output terminal of the first circuit and potentialdifferent from the predetermined potential; a third circuit forgenerating an output signal of the predetermined potential in accordancewith a second level of a clock signal, and for setting an outputterminal to the high impedance state in accordance with a first level ofthe clock signal; a fourth circuit for generating an output signal inaccordance with the output potential of the third circuit with a secondimpedance element disposed between the output terminal of the thirdcircuit and potential different from the predetermined potential; and afifth circuit for generating a clock signal detection result based onthe output signals of the second and the fourth circuit.

[0016] In the above circuits, each of the first and the second impedanceelements can be arranged to include one of an external resistor, and aresistor and a transistor formed inside the semiconductor integratedcircuit.

[0017] According to the present invention, the output signal of thefirst circuit that generates the output signal of predeterminedpotential in accordance with a first level of a clock signal, and setsan output terminal to the high impedance state in accordance with asecond level of the clock signal is smoothed, and then used to detectthe clock signal. Thus, it is possible to reliably detect whether or notthe clock signal is supplied with a reduced circuit scale and withreduced power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a view showing a clock signal detection circuitaccording to a first embodiment of the present invention.

[0019]FIG. 2 is a circuit diagram showing a configuration of thetristate buffer circuit shown in FIG. 1.

[0020]FIG. 3 is a waveform chart showing waveforms at various points inthe circuit shown in FIG. 1.

[0021]FIG. 4 is a view showing a clock signal detection circuitaccording to a second embodiment of the present invention.

[0022]FIG. 5 is a view showing a clock signal detection circuitaccording to a third embodiment of the present invention.

[0023]FIG. 6 is a view showing a clock signal detection circuitaccording to a fourth embodiment of the present invention.

DETAILED DESCRIPTION

[0024] Hereinafter, preferred embodiments of the present invention willbe described referring to the accompanying drawings.

[0025]FIG. 1 is a view showing a configuration of a clock signaldetection circuit according to a first embodiment of the presentinvention, As shown in FIG. 1, this clock signal detection circuitincludes (inside the semiconductor integrated circuit) an inverter 1 forinverting a clock signal CK, tristate buffer circuit 2 having an outputenable terminal to which the clock signal inverted by the inverter 1 issupplied, and a buffer circuit 3 to which an output signal of thetristate buffer circuit 2 is input. The output signal from the tristatebuffer circuit 2 is also supplied to a terminal (a pad) 4 of thesemiconductor integrated circuit. An external resistor, as an impedanceelement, is disposed between the pad 4 and the earth potential (ground).

[0026]FIG. 2 is a circuit diagram showing a configuration of thetristate buffer circuit shown in FIG. 1. As shown in FIG. 2, tristatebuffer circuit 2 is provided with a P channel MOS transistor QP1 and a Nchannel MOS transistor QN1 that form an inverter, a P channel MOStransistor QP2 and a N channel MOS transistor QN2 for respectivelysupplying source current to transistors QP1 and QN1, and an inverter 20for inverting an output enable signal OE bar of the negative-true logicto output an output enable signal OE.

[0027] The transistor QP2 is disposed between the higher power sourcepotential V_(DD) and performs switching in accordance with the outputenable signal OE bar of the negative-true logic applied to an outputenable terminal 22. In contrast, the transistor QN2 is disposed betweenthe transistor QN1 and the lower power source potential V_(SS) (assumedto be the earth potential in the present embodiment) and performsswitching in accordance with the output enable signal OE output from theinverter 20.

[0028] When the output enable signal OE bar of the negative-true logicis in the low level, the transistors QP2 and QN2 turn on to cause thetransistors QP1 and QN1 to operate as an inverter that inverts inputsignal IN applied to an input terminal 21 and output the inverted signalfrom an output terminal 23 as an output signal OUT.

[0029] In contrast, when the output enable signal OE bar of thenegative-true logic is in the high level, the transistors QP2 and QN2turn off to cause the transistors QP1 and QN1 to turn off resulting inthe high-impedance state of the output terminal 23 independent of thestate of the input signal IN applied to the input terminal 21.

[0030] Referring to FIG. 1 again, the earth potential is supplied to theinput terminal of the tristate buffer circuit 2 for providing thereto alow level input signal. The tristate buffer circuit 2 inverts the lowlevel input signal to generate the high level output signal when theclock signal CK is in the high level, and makes the output terminal bein the high impedance when the clock signal is in the low level.

[0031] The resistor 5 is disposed between the pad 4 and the earthpotential. In general, an equivalent circuit of a resistor includes aresistance component and a capacitance component connected in parallelto the resistance component, Further, the tristate buffer circuit 2 hasoutput capacitance, and the buffer circuit has input capacitance,Furthermore, there is stray capacitance in interconnection wiring.Accordingly, there is also provided a capacitance component in additionto the resistance component between the pad 4 and the earth potential.

[0032] Electric potential of the pad 4 (hereinafter referred to as padpotential) V_(p) is integrated (smoothed) by the resistance componentand the capacitance component mentioned above when the output terminalof the tristate buffer circuit 2 is in the high impedance state. Thebuffer circuit 3 outputs a detection signal DET in accordance with theoutput level of the tristate buffer circuit 2, namely the pad potentialV_(P).

[0033]FIG. 3 is a waveform chart showing waveforms at various points inthe circuit shown in FIG. 1. While the clock signal CK is supplied, thehigh level of the clock signal CK causes the high level in the padpotential V_(P) because the output signal of the tristate buffer circuit2 is supplied thereto, and during the clock signal CK is in the lowlevel, the pad potential V_(P) smoothly drops by a discharge through theresistor 5.

[0034] In contrast, when the clock signal CK is held to the low level,the output terminal of the tristate buffer circuit 2 is held in the highimpedance state causing the pad potential V_(P) to approach the earthpotential by discharging through the resistor 5. Assuming that an inputlevel that causes the output level of the buffer circuit 3 to be changedto the other level is a threshold level V_(TH), the detection signal DETis in the high level while the pad potential V_(P) is higher than thethreshold level V_(TH), but when the pad potential V_(P) goes below thethreshold level V_(TH), the detection signal DET also goes to the lowlevel. Thus, it is possible to reliably detect whether or not the clocksignal CK is supplied with a simple circuit configuration.

[0035] Next, a second embodiment of the present invention will bedescribed.

[0036]FIG. 4 is a view showing a configuration of a clock detectioncircuit according to the second embodiment of the present invention. Inthe present embodiment, the higher power source potential V_(DD) issupplied to the input terminal of the tristate buffer circuit 2, and theresistor 5 is disposed between the pad 4 and the power source potentialV_(DD). The other portion of the configuration not mentioned here issubstantially the same as in the first embodiment.

[0037] The tristate buffer circuit 2 inverts the high level of the inputsignal to generate the low level output signal when the clock signal CKis in the high level, and when the clock signal CK is in the low level,the tristate buffer circuit 2 changes a state of its output terminal tothe high impedance state. While the clock signal CK is supplied, thehigh level of the clock signal CK causes the low level of the padpotential V_(P) because the output potential of the tristate buffercircuit 2 is applied thereto, and during the time the clock signal CK isheld in the low level, the pad potential V_(P) smoothly increases bycharging through the resistor 5.

[0038] In contrast, when the supply of the clock signal CK stops, thepad potential V_(P) approaches the power source potential V_(DD) bycharging through the resistor 5. While the pad potential V_(P) is belowthe threshold level V_(TH), the detection signal DET remains in the lowlevel, but when the pad potential V_(P) exceeds the threshold levelV_(TH), the detection signal DET is switched to the high level. Thus,with a simple circuit configuration, it is possible to reliably detectwhether or not the clock signal CK is supplied thereto.

[0039] In the above embodiments, the resistor 5 is provided externally.However, the resistor 5 can be formed inside the semiconductorintegrated circuit. Alternatively, a transistor can also be used insteadof the resistor.

[0040] Next, a third embodiment of the present invention that uses atransistor as the impedance element will be described.

[0041]FIG. 5 is a view showing a configuration of a clock signaldetection circuit according to the third embodiment of the presentinvention. As shown in FIG. 5, an N channel MOS transistor 6 is disposedbetween the output terminal of the tristate buffer circuit 2 and theearth potential. Since the gate of the transistor 6 is provided with apredetermined bias voltage V_(B), electric current corresponding to thebias voltage V_(B) flows in the transistor 6, which is equivalent to theresistor.

[0042] In general, transistors have capacitance components between thedrain and the gate, and between the gate and the source. Furthermore,the tristate buffer circuit 2 has the output capacitance, and the buffercircuit 3 has the input capacitance. In addition, there is the straycapacitance around the interconnection wiring. Accordingly, theresistance component and the capacitance component are disposed betweenthe output terminal of the tristate buffer circuit 2 and the earthpotential.

[0043] When the output terminal of the tristate buffer circuit 2 is inthe high impedance state, the output potential thereof is integrated(smoothed) by the resistance component and the capacitance componentmentioned above. The buffer circuit 3 outputs the detection signal DETin accordance with the output potential of the tristate buffer circuit2. Regarding the overall operation, description for the first embodimentcan substantially be applied to the present embodiment. According to thepresent embodiment, the clock signal detection circuit can be realizedwithout using the resistor 5, a passive element (See FIG. 1.).

[0044] Next, a fourth embodiment of the present invention will bedescribed.

[0045]FIG. 6 is a view showing a configuration of a clock signaldetection circuit according to the fourth embodiment of the presentinvention. As shown in FIG. 6, this clock signal detection circuit, inaddition to the circuit of the first embodiment shown in FIG. 1,includes (inside the semiconductor integrated circuit) a tristate buffercircuit 6 whose output enable terminal is provided with the clock signalCK, a buffer circuit 7 to which the output signal of the tristate buffercircuit 6 is input, and an AND circuit 10 to which the output signals ofthe buffer circuits 3 and 7 are input. The output signal of the tristatebuffer circuit 6 is also supplied to a pad 8 of the semiconductorintegrated circuit. An external resistor 9 as an impedance element isdisposed between the pad 8 and the earth potential.

[0046] The earth potential is supplied to the input terminal of thetristate buffer circuit 6 to provide the input terminal with the lowlevel input signal. The tristate buffer circuit 6 inverts the low levelof the input signal to generate the high level signal as an outputsignal when the clock signal CK is in the low level, and when the clocksignal is in the high level, the tristate buffer circuit 6 sets theoutput terminal to the high impedance state

[0047] In addition to a resistance component of the resistor 9, variouscapacitance components are provided between the pad 8 and the earthpotential such as a capacitance component of the resistor 9, an outputcapacitance of the tristate buffer circuit 6, an input capacitance ofthe buffer circuit 7, and stray capacitance along the interconnectionwiring. Electric potential of the pad 8 (hereinafter referred to as padpotential) V_(Q) is integrated (smoothed) by the resistance componentsand the capacitance component mentioned above when the output terminalof the tristate buffer circuit 6 is in the high impedance state. Thebuffer circuit 7 generates an output signal in accordance with theoutput potential of the tristate buffer circuit 6, namely the padpotential V_(Q).

[0048] While the clock signal CK is supplied, the low level of the clocksignal CK causes the high level of the pad potential V_(Q) because theoutput potential of the tristate buffer circuit 6 is applied thereto,and during the time the clock signal CK is held in the high level, thepad potential V_(Q) smoothly decreases by discharging through theresistor 9.

[0049] In contrast, when the clock signal CK stops in the high level,the output terminal of the tristate buffer circuit 6 is set to the highimpedance state causing the pad potential V_(Q) to approach the earthpotential by discharging through the resistor 9. Assuming that an inputlevel that causes the output level of the buffer circuit 7 to be changedto the other level is a threshold level V_(TH7), the output potential ofthe buffer circuit 7 is the high level while the pad potential V_(Q) ishigher than the threshold level V_(TH7), but when the pad potentialV_(Q) goes below the threshold level V_(TH7), the output potential ofthe buffer circuit 7 also goes to the low level.

[0050] Also, the buffer circuit 3 generates an output signal inaccordance with the output potential of the tristate buffer circuit 2,namely the pad potential V_(P). When the clock signal CK stops in thelow level, the output terminal of the tristate buffer circuit 2 is setto the high impedance state causing the pad potential V_(P) to approachthe earth potential by discharging through the resistor 5. Assuming thatan input level that causes the output level of the buffer circuit 3 tobe changed to the other level is a threshold level V_(TH3), the outputpotential of the buffer circuit 3 is the high level while the padpotential V_(P) is higher than the threshold level V_(TH3), but when thepad potential V_(P) goes below the threshold level V_(TH3), the outputpotential of the buffer circuit 3 also goes to the low level.

[0051] Since the output signals of the buffer circuit 3 and 7 are inputto the AND circuit 10, when the clock signal CK stops in either the highlevel or the low level, either one of the output signals of the buffercircuits 3 and 7 becomes the low level, and accordingly, the detectionsignal DET output from the AND circuit 10 becomes the low level. In thismanner, according to the present embodiment, even if the clock signal CKstops in either the high level or low level, it is possible to detectthat supply of the clock signal CK stops. Note that in the presentembodiment a resistor formed inside the semiconductor integrated circuitor an impedance element such as transistor can also be used instead ofthe resistor 5 and/or 9.

What is claimed is:
 1. A clock signal detection circuit, comprising: afirst circuit generating an output signal of predetermined potential inaccordance with a first level of a clock signal, and setting an outputterminal to a high impedance state in accordance with a second level ofthe clock signal; an impedance element disposed between the outputterminal of the first circuit and a potential source having a potentialthat is different from the predetermined potential; and a second circuitgenerating a clock signal detection result in accordance with an outputpotential of the first circuit.
 2. A clock signal detection circuit,comprising: a first circuit generating a first output signal ofpredetermined potential in accordance with a first level of a clocksignal, and setting an output terminal of the first circuit to a highimpedance state in accordance with a second level of the clock signal; afirst impedance element disposed between the output terminal of thefirst circuit and a first potential source having a potential that isdifferent from the predetermined potential; a second circuit generatinga second output signal in accordance with an output potential of thefirst circuit; a third circuit generating a third output signal with thepredetermined potential in accordance with the second level of the clocksignal, and setting an output terminal of the third circuit to the highimpedance state in accordance with the first level of the clock signal;a second impedance element disposed between the output terminal of thethird circuit and a second potential source having a potential that isdifferent from the predetermined potential; a fourth circuit generatinga fourth output signal in accordance with an output potential of thethird circuit; and a fifth circuit generating a clock signal detectionresult based on output signals of the second and the fourth circuit. 3.A clock signal detection circuit according to claim 1, wherein theimpedance element includes one of a resistor and a transistor.
 4. Aclock signal detection circuit according to claim 2, wherein at leastone of the first and second impedance elements includes one of aresistor and a transistor.
 5. A semiconductor integrated circuit,comprising: a first circuit generating an output signal of apredetermined potential in accordance with a first level of a clocksignal, and setting an output terminal to a high impedance state inaccordance with a second level of the clock signal; and a second circuitgenerating a clock signal detection result in accordance with an outputpotential of the first circuit with an impedance element disposedbetween the output terminal of the first circuit and a potential sourcehaving a potential that is different from the predetermined potential.6. A semiconductor integrated circuit, comprising: a first circuitgenerating a first output signal of a predetermined potential inaccordance with a first level of a clock signal, and setting an outputterminal of the first circuit to a high impedance state in accordancewith a second level of the clock signal; a second circuit for generatinga second output signal in accordance with an output potential of thefirst circuit with a first impedance element disposed between the outputterminal of the first circuit and a first potential source having apotential that is different from the predetermined potential; a thirdcircuit generating a third output signal of the predetermined potentialin accordance with a second level of the clock signal, and setting anoutput terminal of the third circuit to the high impedance state inaccordance with the first level of the clock signal; a fourth circuitgenerating a fourth output signal in accordance with an output potentialof the third circuit with a second impedance element disposed betweenthe output terminal of the third circuit and a second potential sourcehaving a potential that is different from the predetermined potential;and a fifth circuit generating a clock signal detection result based onoutput signals of the second and the fourth circuit.
 7. A semiconductorintegrated circuit according to claim 5, wherein the impedance elementincludes one of: an external resistor; and a resistor and a transistorformed inside the semiconductor integrated circuit.
 8. A semiconductorintegrated circuit according to claim 6, wherein at least one of thefirst and second impedance elements includes one of: an externalresistor; and a resistor and a transistor formed inside thesemiconductor integrated circuit.